MSc Fei Wang
Electronic Instrumentation (EI), Department of Microelectronics
Expertise: DATA converter, CMOS sensorThemes: CMOS Image Sensors
Fei Wang received his MS degree from SEU in 2009, in microelectronics engineering. During his Master's, he worked on developing a CMOS nerve signal detector and processing circuit. After worked several years in industry on different types of data converters. He joined the Electronic Instrumentation Laboratory at TU Delft to continue his research interests in integrated circuit design and smart sensors.
- Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity
Fei Wang; Albert Theuwissen;
IEEE Transactions on Circuits and Systems I: Regular Papers,
Volume 66, Issue 3, pp. 930--940, March 2019. DOI: 10.1109/tcsi.2018.2872627
Abstract: ...In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18-μm, 1-poly, and 4-metal CIS technology with a pixel array of 128×160 is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor C FD on the floating diffusion node, which is remnant in VM.
Last updated: 8 Feb 2019
- Left in 2018