MSc thesis project proposal

[2022] Sub-100fs 24-30GHz Sub-Sampling Phase-Locked Loop Design for Wireless and Wireline Applications

High-performance phased-locked loop (PLL) designs are critical components for generating clean clocks for wireline communications, wireless communications, and processors.  For example, in 5G wireless systems and SerDes running above 200Gb/s,  the clocks synthesizers between 20GHz and 30GHz are widely used. In addition to the stringent phase noise and RMS jitter requirements, the designers would like to take as less power as possible.

Among all the PLL architectures,  the sub-sampling PLL (SSPLL) relieves the power and jitter trade-off, by reducing the CP noise contribution with increased PD gain. As a result, the FOM values of  integer-N SSPLLs reaches below -250dB. However, this FOM target is still difficult for fractional-N PLLs running between 20GHz to 30GHz.

Several fractional-N PLLs based on sub-sampling or sampling techniques have been proposed in these years to reduce the power and improve the jitter performance [1],[2].  However, extra power is consumed due to the non-idealities of DTC and its calibration circuits. In this project, out target is to design a 20-30GHz factional-N SSPLL based on a integer-N SSPLL, with FOM value less than -253dB.  By exploring novel digital-to-time converter architectures, and hybrid SSPLL systems, we are hoping to design a fractional-N PLL better than state-of-the-art.

In this project, you will cooperate with researchers from UC Berkeley, USA. Using Berkeley Analog Generator (BAG) as the design tool is also an option, by which you can generate analog and mixed-signal circuit with Python, and explore the agile analog circuit design methodologies. Some successful state-of-the-art designs by BAG are presented in [3] and [4]

About BAG:

Berkeley Analog Generator is an integrated framework for the development of generators of Analog and Mixed Signal (AMS) circuits, developed at UC Berkeley. Such generators are parameterized design procedures that produce sized schematics and correct layouts optimized to meet a set of input specifications. BAG extends previous work by implementing interfaces to integrate all steps of the design flow into a single environment and by providing helper classes - both at the schematic and layout level - to aid the designer in developing truly parameterized and technology-independent circuit generators. This simplifies the codification of common tasks including technology characterization, schematic and testbench translation, simulator interfacing, physical verification and extraction, and parameterized layout creation for common styles of layout. This approach will foster design reuse, ease technology migration, and shorten time-to-market, while remaining close to the classical design flow to ease adoption.

BAG have been used in UC Berkeley to design generators for several circuits, including a SerDes and SAR ADC in 16nm and a SerDes Transmitter in 28nm.  Many IC design companies, including Intel, Xilinx and NXP have adopted BAG in their product and research teams, developing circuits, such as LDO, ADC and SerDes, etc.

Related links:
https://bag-framework.readthedocs.io/en/latest/
https://ieeexplore.ieee.org/document/6691100

[1] D. Liao and F. F. Dai, “A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation,” IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 694–704, Mar. 2021.

[2] A. Tharayil Narayanan et al., “A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB,” IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1630–1640, Jul. 2016.

[3] M. Choi et al., "8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 128-130.

[4] Z. Wang et al., "An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS," in IEEE Journal of Solid-State Circuits.

Assignment

  1. Literature review of PLL fundamentals  and architectures.
  2. Design of a high performance fractional-N SSPLL based on an integer-N SSPLL already been verified, including the design of DTC and system simulation.
  3. Tape-out is possible depending on the design and available time.

Requirements

You should be familiar with analog IC design and Cadence environment. If you are interested, please send your CV, BSc transcripts and MSc grades (obtained to date) to Sijun Du at email: Sijun.Du@tudelft.nl

Contact

dr. Sijun Du

Electronic Instrumentation Group

Department of Microelectronics

Last modified: 2022-01-06